1. Field of the Invention
This invention relates to a method of utilizing common buses in a multiprocessor system in which a main storage is divided into a plurality of banks, and a plurality of common buses are provided.
2. Description of the Prior Art
Common buses in a multiprocessor system have been widely used as information transmission means among units having a high cost performance. In most cases, from an electrical point of view, the bus comprises a lead wire. At a certain time period, a unit trying to transmit information occupies the bus, and at least one unit trying to receive information receives the information. Since variations are present in the transmission of information between units in a system, the high cost performance of the common bus resides in that a single hardware, i.e., the bus, is used for all transmission of information. However, for various reasons, particularly because of reduced instruction set computers (RISCs), the bandwidth of the bus, particularly, a memory bus for connecting a CPU to a main storage, has become incapable of keeping up with the supply of data resulting from increase in speed of the CPU.
In order to solve such a problem, there have been adopted a method wherein a CPU is connected to a main storage by a network having a more complicated structure than a bus, a method wherein a CPU is connected to a main storage via a plurality of buses wherein the main storage is divided into a plurality of banks, and the buses are addressed differently, and a method wherein the data width of a bus is widened, and the like.
The above-described conventional methods, however, have the following problems.
In the method wherein a CPU is connected to a main storage by a network having a complicated structure, the cost is higher than when using a plurality of buses. In the method wherein a main storage is divided into a plurality of banks with different addresses, a dedicated bus can be allocated to each bank. Since buses are fixedly allocated in accordance with their addresses, dispersion of load among buses cannot be obtained. As a result, a situation may arise such that, while a certain bus is busy, the rate of utilization of other buses is low. In the method wherein the data width of a bus is widened, access might be concentrated on a particular memory bank.